Why it's awesome to work with US
Qualified Team:
Our management team combines the experiences of executives.
The management consist of directors having 20+ years experience in creating business and managing team of ~100 persons
An Advisory board with extensive backgrounds in managing and developing successful businesses within the industry.
Experienced Peple:
The management has design managers and R&D operations head with 15+ years experience managing various range of systems working well in numerous applications, with numerous patents and publications record.
Interested?
We are looking for passionate people from 0-10 Years of experience in Analog/RF circuit and layout design.Try reaching us through email hr_at_vervesemi.com or use the contact form below. We will get back to you.
Past Publications
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2007 Custom Integrated Circuits Conference. CICC'07. IEEE, 189-192
20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process
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2008 IEEE Custom Integrated Circuits Conference
A 1.2 v 11b 100Msps 15mW ADC realized using 2.5 b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process
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2011 VLSI Circuits (VLSIC), 2011 Symposium on, 64-65
A 3GS/s, 9b, 1.2 V single supply, pure binary DAC with> 50dB SFDR up to 1.5 GHz in 65nm CMOS
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2013 Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian, 81-84
A 12b 1.7 GS/s two-times interleaved DAC with<-62dBc IM3 across Nyquist using a single 1.2 V supply
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2016 ESSCIRC (European Solid State Circuit Conference)
A 0.065mm2 19.8mW Single channel calibration-free 12b 600Ms/s ADC in 28nm UTBB FDSOI FDSOI USING FBB
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2017 ESSCIRC Paper invited for JSSC, Jul-17 Edition