Our management team combines the experiences of executives.
The management consist of directors having 20+ years experience in creating business and managing team of ~100 persons
An Advisory board with extensive backgrounds in managing and developing successful businesses within the industry.
The management has design managers and R&D operations head with 15+ years experience managing various range of systems working well in numerous applications, with numerous patents and publications record.
We are looking for passionate people from 0-10 Years of experience in Analog/RF circuit and layout design.Try reaching us through email hr_at_vervesemi.com or use the contact form below. We will get back to you.
20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process
A 1.2 v 11b 100Msps 15mW ADC realized using 2.5 b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process
A 3GS/s, 9b, 1.2 V single supply, pure binary DAC with> 50dB SFDR up to 1.5 GHz in 65nm CMOS
A 12b 1.7 GS/s two-times interleaved DAC with<-62dBc IM3 across Nyquist using a single 1.2 V supply
A 0.065mm2 19.8mW Single channel calibration-free 12b 600Ms/s ADC in 28nm UTBB FDSOI FDSOI USING FBB